The semiconductor industry has seen tremendous advances in technology in recent years which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
Flip chip technology answers the demand for improved input/output (I/O) connections from the chip to external systems. On a flip chip, the electrical components are located (face down) on the side of the die which attaches to the chip package. In this manner, the flip chip provides a short interconnection length using, for example, ball-grid array (BGA) solder connections. The self-aligning nature of the solder bumps offers the advantages of higher density mounting, improved electrical performance and reliability, and better manufacturability. The positioning of the circuit side is the source of many advantages in the flip chip design. However, in other regards, the orientation of the die with the circuit side face down on a substrate is a disadvantage.
In example, access to the circuit region is necessitated in order to modify or debug a finished chip. Additionally, access to the circuit region is often desired through manufacturing stages in order to test and analyze the circuit's integrity. In this event, it is necessary to cut through the body of the flip chip die or through the chip package in order to access the circuit region.
Various methods have been employed to access the circuit region. A popular method includes milling or grinding off portions of the die, or the chip packaging in order to access the circuit region. This method is not adequate, however, for all circuit testing purposes. The difficulty resides in the accuracy of this method as well as the wear the technique places on the circuit region. An example is provided with the need to study the quality of the electrical contacts in the circuit region or, conversely, to resolve the source of contact problems. A great deal of precision is needed to access specific regions of the contact. Fast milling simply is too rough a technique and may even add defects to the contact in the approach. When this happens it may be impossible to uncover the original flaw in the contact. Also, slow milling techniques are simply too inefficient for mass fabrication design testing and analysis.
For these reasons, it is necessary to uncover an alternative method and device for accessing the circuit region on a flip chip die. More specifically, an alternative method and device are needed to access and study the electrical contacts between the flip chip die and the chip package. The new method and device must avoid adding defects to the regions intended for analysis.